Method of monitoring computer elements, particularly microprocessors

ABSTRACT

A method is proposed which serves to enable recognition, in microprocessors (1) provided with a monitoring device (2) having a signal generator stage for reset signals, of whether a reset signal was effected by the monitoring device (2) or by a power-on reset circuit (5). To this end, a comparison is performed between a comparison pattern stored in a non-erasable memory zone (6) and a pattern, which is typical of resetting erected by the monitoring device (2), located in an erasable memory zone (7).

STATE OF THE TECHNOLOGY

The invention relates generally to a method for monitoring computerelements, particularly microprocessors, and more particularly toimproving processor efficiency by distinguishing between interrupts andpower failures using a single input pin of the chip.

BACKGROUND:

From German Patent Disclosure Documents DE-OS No. 28 42 892 and DE-OSNo. 29 03 638, monitoring devices for program controlled equipment areknown which recognize short duration disturbances or system breakdownsand thereupon actuate a reset or interrupt input of a microprocessor.This stops the then-running program, which by resetting is put back intoproper operation at the beginning of the program, so that an emergencycircuit arrangement can be actuated. In such an arrangement, it is aproblem that it is impossible to distinguish whether a reset has beenbrought about by the monitoring device (so-called "watchdog reset") orby other causes, for instance by switching on the supply voltage(so-called "power-on-reset").

In order to attain a definite status after switching on the supplyvoltage, from which status a normal program course can be started, theemergency circuit arrangement must first be connected to themicroprocessor after a stable microprocessor state has been attained.Because of circuitry or program controlled provisions, it is necessaryfor the connection of the monitoring device to take place in such a waythat a reset signal of the monitoring device will not immediately stopthe microprocessor and start it up again.

From German Patent Disclosure Document DE-OS No. 32 40 704, a circuitarrangement for monitoring computer elements is know which, forlonger-lasting disturbances, keeps attempting to restart the program ofthe element by means of reset signals. Here also, the problem existsthat it is impossible to distinguish between a reset caused by switchingon the power, or by the actuation of a reset key, and a reset broughtabout by a monitoring device.

THE INVENTION

The method according to the invention for monitoring computer elements,particularly microprocessors, has the advantage over the prior art thatby means of a simple program controlled decision at the beginning of theportion of the program that follows resetting, it is possible torecognize whether the reset was triggered unconditionally, or by theactivity of a monitoring device. Since this decision is made underprogram control by the microprocessor, it is readily possible toimplement changes or make further decisions in the decision-makingprocess. This has the advantage of shortening the restarting of theprogram considerably, because a complete reinitializing of the registersand reloading of the user program are no longer necessary. It is alsoadvantageous that a decision according to the method of the inventioncan be made without requiring any special technical circuitry.

DRAWING

An exemplary embodiment is shown in the drawing and explained in furtherdetail in the ensuing description.

FIG. 1 is a circuit diagram of an apparatus for performing the method;and

FIG. 2 is a signal diagram explaining its operation.

DESCRIPTION OF THE EXEMPLARY EMBODIMENT

FIG. 1 shows a microprocessor (MP) 1, a monitoring device (watchdog) 2,a power-on reset circuit (PO) 5, a fixed value memory (ROM) 6 and anerasable memory (RAM) 7.

The microprocessor 1 is connected via a bus at one output 13 to thefixed value memory 6 and the erasable memory 7. One output 11 of themicroprocessor 1 is connected to one input 21 of the watchdog 2, theoutput 22 of which is connected to one input of an OR element 4. Afurther input of the OR element 4 is connected to one output 51 of thepower-on reset circuit 5, and the output of the OR element leads to oneinput 12 of the microprocessor 1.

Via the output 11, the microprocessor 1 furnishes statisticallydistributed signals in a definite frequency range to the watchdog 2 in aknown manner. If the signal is outside this frequency range or datarate, for instance when operation is stopped, then an endless loop orindefinite program course of the microprocessor 1 is involved, which isrecognized by the watchdog 2, which thereupon triggers a conditionalreset via the OR element 4. When the supply voltage is switched on, anunconditional reset is triggered by the power-on reset circuit 5 via theOR element 4.

As shown in FIG. 2, in its normal state the microprocessor 1 is in aloop between a main program 60, in which at least one pulse is formed atthe output 11, and a reset interrogation 61 by an interrogation of theinput 12. It does not matter whether this interrogation, in the type ofmicroprocessor selected for a specific application, is realized by meansof a program or by means of circuitry. Thus if no reset ("0") ispresent, then operation continues in the main program 60.

When a reset ("1") is present, a (bit) pattern comparison makes itpossible to recognize whether a reset is effected by the watchdog 2 orby the power-on reset circuit 5. In the case of a power-on reset, anindefinite pattern is present in the erasable memory of themicroprocessor 1. In the case of a watchdog reset, a pattern that istypical of the previous history of a watchdog reset, which is known apriori, is present in at least a small portion of the erasable memory.For the comparison 62, a comparison pattern corresponding to thistypical pattern is loaded from the fixed value memory 6 and comparedwith the pattern in the particular erasable memory involved. If there isequality, or typical partial equality, of these patterns ("1"), atransfer is made to a program section 64, which performs a taskassociated with the watchdog reset and reactivates the watchdog 2 viathe output 11 of the microprocessor 1. Upon non-equality of the patterns("0"), a transfer is made to a program section 63, which has to do withthe power-on reset and brings about a reinitialization 65 of the entiresystem. After programs 63, 65 or 64 have been completed, the apparatusof FIG. 1 is once again in the program status 60, 61 shown in FIG. 2.

I claim:
 1. Method for monitoring computer elements (1), particularlymicroprocessors, having a reset input (12), a volatile or eraseablememory (7), a non-volatile or non-eraseable memory (6), input/outputport means (13) connecting said memories to the computer element (1),amonitoring device (2) for the computer element (1) which device causes aresetting of the computer element (1), comprising the steps of detectinga reset signal on said reset input (12), performing a comparison (62)between a comparison pattern stored in said non-eraseable memory (6) anda pattern present in said eraseable memory (7); and performing,selectively, one of a complete re-initialization (65) of saidmicroprocessor and a shorter program sequence (64) in dependence uponwhether said comparison indicates that the pattern in said volatile oreraseable memory is random.
 2. Method according to claim 1,characterized in that if there is at least partial equality between thepattern and the comparison pattern, a program (64) is carried out whichexecutes a function associated with a reset caused by the monitoriingdevice (2).
 3. Method according to claim 2, characterized in that thefunction includes an activation of the monitoring device (2). 4.Computer apparatus, for performing a method according to any one of theforegoing claims, havingsaid reset input (12), said monitoring device(2) for the computer element (1) which device causes a resetting of thecomputer element (1), said volatile or eraseable memory (7), saidnon-volatile or non-eraseable memory (6), said input/output port means(13) connecting said memories to the computer element (1), a power-oncircuit (5), and a logical linking device (4), wherein both themonitoring device (2) and the power-on reset circuit (5) are connectedto inputs of said logical linking element (4), and the output of thelogical linking element (4) is connected to said reset input (12) of thecomputer element (1).